Buses and Interfaces

Overview

A bus is a shared communication channel connecting various components in a computer system. In robot systems, buses connect CPUs, memory, sensors, and actuators, serving as the "highway" for data flow. Understanding bus architecture is essential for diagnosing communication bottlenecks and designing efficient systems.

System Bus Fundamentals

Three Types of Buses

A system bus consists of three sets of signal lines:

Bus Type	Function	Signal Direction
Address Bus	Specifies memory/peripheral addresses	CPU -> Memory/Peripherals
Data Bus	Transfers data	Bidirectional
Control Bus	Transfers control signals (read/write/interrupt)	Bidirectional

Address bus width determines the addressable range:

\[ \text{Addressable Space} = 2^n \text{ bytes} \]

Where \(n\) is the number of address bus bits. For example, a 32-bit address bus can address \(2^{32} = 4\text{GB}\).

Bus Bandwidth

\[ \text{Bus Bandwidth} = \text{Data Bus Width} \times \text{Bus Frequency} \times \text{Transfers per Cycle} \]

DDR5 Memory Bus Bandwidth

Data width = 64 bits = 8 bytes, frequency = 4800MHz, DDR (double data rate):

\[\text{Bandwidth} = 8 \times 4800 \times 10^6 \times 2 = 76.8 \text{ GB/s}\]

Bus Architecture

Traditional Bus Architecture

graph TB
    CPU[CPU] --> NB[North Bridge]
    NB --> RAM[Memory DRAM]
    NB --> GPU[GPU<br>PCIe x16]
    NB --> SB[South Bridge]
    SB --> USB[USB]
    SB --> SATA[SATA SSD]
    SB --> ETH[Ethernet]
    SB --> AUDIO[Audio]

Modern SoC Bus Architecture

Modern SoCs (such as ARM chips) use on-chip interconnects:

graph TB
    subgraph SoC
        CPU[CPU Cluster<br>Cortex-A78] --> AXI[AXI Interconnect<br>High-Performance Bus]
        GPU[GPU] --> AXI
        NPU[NPU/DLA] --> AXI
        AXI --> MC[Memory Controller<br>LPDDR5]
        AXI --> APB[APB Bridge<br>Low-Speed Peripheral Bus]
        APB --> UART[UART]
        APB --> I2C[I2C]
        APB --> SPI[SPI]
        APB --> GPIO[GPIO]
        AXI --> AHB[AHB Bridge]
        AHB --> DMA[DMA Controller]
        AHB --> USB_C[USB Controller]
        AHB --> ETH_C[Ethernet Controller]
    end

    MC --> MEM[LPDDR5 Memory]

PCIe (Peripheral Component Interconnect Express)

PCIe Fundamentals

PCIe is the modern high-speed serial bus standard:

Version	Per-Lane Bandwidth	x4 Bandwidth	x16 Bandwidth	Encoding
PCIe 3.0	1 GB/s	4 GB/s	16 GB/s	128b/130b
PCIe 4.0	2 GB/s	8 GB/s	32 GB/s	128b/130b
PCIe 5.0	4 GB/s	16 GB/s	64 GB/s	128b/130b

PCIe Applications in Robotics

Device	Interface	Lanes	Use
NVMe SSD	PCIe 3.0/4.0	x4	Data logging
GPU (desktop)	PCIe 4.0/5.0	x16	Deep learning training
Ethernet card	PCIe 3.0	x1/x4	High-speed network communication
FPGA accelerator	PCIe 3.0/4.0	x4/x8	Sensor preprocessing

PCIe on Jetson

Jetson Orin has multiple PCIe lanes:

• PCIe Gen4 x8 (can be split into x4+x4)
• Used for connecting NVMe SSDs, Ethernet cards, and other expansion devices

USB (Universal Serial Bus)

USB Version Comparison

Version	Speed	Encoding	Power	Robotics Use
USB 2.0	480 Mbps	NRZI	5V/0.5A	Low-speed cameras, serial devices
USB 3.0	5 Gbps	8b/10b	5V/0.9A	RGB cameras, LiDAR
USB 3.1	10 Gbps	128b/132b	5V/3A (Type-C)	Depth cameras
USB 3.2	20 Gbps	128b/132b	5V/3A	High-speed data transfer

Common USB Issues in Robotics

USB Bandwidth Sharing

Devices under the same USB Host Controller share bandwidth. For example:

• Two cameras (each needing 200MB/s) connected to a USB 3.0 Hub
• Total bandwidth 500MB/s -- both cameras may experience frame drops

Solution: Use different USB controllers, or use the CSI interface

# View USB topology on Linux
lsusb -t

# Check USB device bandwidth allocation
cat /sys/bus/usb/devices/*/bAlternateSetting

AXI Bus (ARM AMBA)

AMBA Bus Family

ARM's AMBA (Advanced Microcontroller Bus Architecture) is the standard bus protocol inside SoCs:

Bus	Features	Bandwidth	Use
AXI	High-performance, burst transfers	Very high	CPU<->Memory, GPU<->Memory
AHB	Medium performance	Medium	DMA, USB controller
APB	Low power, simple	Low	UART, I2C, SPI, GPIO

Key AXI Features

• Separate read and write channels: Read and write can occur simultaneously
• Burst Transfer: One address, continuous transfer of multiple data words
• Outstanding Transactions: New transfers can be issued before the previous one completes
• Out-of-Order Completion: Transfers with different IDs can complete out of order

AXI 5 Channels:
+-- Write Address Channel (AW) : Master -> Slave
+-- Write Data Channel (W)     : Master -> Slave
+-- Write Response Channel (B) : Slave -> Master
+-- Read Address Channel (AR)  : Master -> Slave
+-- Read Data Channel (R)      : Slave -> Master

Interrupt Handling

Three I/O Modes

Mode	Principle	CPU Usage	Latency	Suitable Scenario
Polling	CPU continuously queries device status	100%	Lowest	Ultra-low latency needs
Interrupt	Device notifies CPU when ready	Low	Medium	Most scenarios
DMA	Hardware transfers data directly	Very low	Higher (initialization)	Large data transfers

Interrupt Handling Flow

graph TD
    A[Peripheral Issues Interrupt Request] --> B[Interrupt Controller NVIC/GIC]
    B --> C{Priority Arbitration}
    C --> D[Save Current Context<br>Push Registers]
    D --> E[Jump to Interrupt Vector Table<br>Execute ISR]
    E --> F[Clear Interrupt Flag]
    F --> G[Restore Context<br>Pop Registers]
    G --> H[Return to Interrupted Program]

ARM Interrupt Controllers

STM32 (Cortex-M) -- NVIC:

• Up to 240 interrupt sources
• Programmable priority (0-255)
• Supports nested interrupts (higher priority can preempt lower priority ISR)
• Interrupt latency: 12 clock cycles (Cortex-M4)

Jetson/RPi (Cortex-A) -- GIC:

• GIC-400/GIC-600
• SGI (Software Generated Interrupts), PPI (Private Peripheral Interrupts), SPI (Shared Peripheral Interrupts)
• Supports routing interrupts to specific cores

Interrupt Priority Design

For robot systems, typical interrupt priority allocation:

Priority	Interrupt Source	Description
Highest	Emergency stop button	Safety-related, must respond immediately
High	Motor encoder	Real-time control requirement
High	IMU data ready	Attitude estimation
Medium	Communication receive (CAN/UART)	Command reception
Low	ADC conversion complete	Voltage/temperature monitoring
Lowest	Timer (LED blinking)	Status indication

ISR Writing Rules

1. Keep it as short as possible: Only do minimal work in the ISR (set flags, copy data)
2. Never block: Cannot call sleep, malloc, etc. in an ISR
3. Never use printf: I/O operations are too slow
4. Use volatile: Variables modified in the ISR should be declared volatile

// Good ISR design
volatile bool imu_data_ready = false;
volatile uint8_t imu_buffer[14];

void IMU_IRQHandler(void) {
    // Only do data copy and flag setting
    memcpy((void*)imu_buffer, (void*)IMU_DATA_REG, 14);
    imu_data_ready = true;
    __HAL_GPIO_EXTI_CLEAR_IT(IMU_INT_PIN);
}

// Process data in the main loop
while (1) {
    if (imu_data_ready) {
        imu_data_ready = false;
        process_imu_data(imu_buffer);
    }
}

I/O Model Comparison

Synchronous vs. Asynchronous

Synchronous Blocking I/O:
Thread: [===Request===][=========Waiting=========][==Process==]

Synchronous Non-blocking I/O (Polling):
Thread: [Request][Check][Check][Check]...[Data Ready][Process]

Asynchronous I/O (Interrupt/DMA):
Thread: [Request][Do other work...][Interrupt!][Process]

Linux I/O Models

Model	Description	Robotics Application
Blocking I/O	read() blocks until data is ready	Simple serial port reading
Non-blocking I/O	read() returns immediately, requires polling	Multi-sensor polling
I/O Multiplexing	select()/poll()/epoll()	Monitor multiple devices simultaneously
Asynchronous I/O	aio_read(), kernel notifies on completion	High-performance data acquisition

# Using select in Python to monitor multiple serial ports
import select

sensors = [serial_imu, serial_lidar, serial_gps]
while True:
    readable, _, _ = select.select(sensors, [], [], timeout=0.01)
    for sensor in readable:
        data = sensor.read(sensor.in_waiting)
        process(data)

Robot Bus Architecture Example

Typical Mobile Robot

graph TB
    subgraph Main Controller[Main Controller - Jetson Orin]
        CPU[CPU<br>Cortex-A78]
        GPU_M[GPU<br>Ampere]
        CSI[CSI Interface]
        PCIE[PCIe]
        USB3[USB 3.0]
        ETH[Gigabit Ethernet]
        UART_M[UART]
    end

    subgraph Sensors
        CAM[RGB-D Camera] -->|CSI/USB3| CSI
        LIDAR[LiDAR] -->|Ethernet| ETH
        IMU[IMU] -->|SPI| MCU
    end

    subgraph MCU_Control[MCU - STM32H7]
        MCU[Cortex-M7]
        CAN_C[CAN Bus]
        PWM[PWM Output]
        ADC_M[ADC]
    end

    UART_M -->|UART 115200| MCU
    MCU -->|CAN| MOTOR1[Motor Driver 1]
    MCU -->|CAN| MOTOR2[Motor Driver 2]
    MCU -->|PWM| SERVO[Servo]
    MCU -->|ADC| BATTERY[Battery Voltage]

    PCIE -->|NVMe| SSD[SSD Storage]

Summary

1. System buses consist of address, data, and control components
2. PCIe is the mainstream standard for high-speed expansion, with bandwidth doubling each generation
3. USB is convenient but watch out for bandwidth sharing issues
4. AXI/AHB/APB form the hierarchical bus system inside ARM SoCs
5. Interrupt mechanisms are the foundation for real-time response; ISRs should be as short as possible
6. DMA frees the CPU during large data transfers

References

• ARM AMBA AXI Protocol Specification
• PCI Express Base Specification
• USB 3.2 Specification
• STM32 Reference Manual: NVIC and Interrupt Handling

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