Skip to content

Instruction Set Architecture (ISA)

1. The Essence of ISA

Instruction Set Architecture is the contract between hardware and software:

  • Defines what operations a processor can execute
  • Defines how operands are accessed
  • Defines how instructions are encoded in binary

An ISA is an abstract specification, independent of any specific implementation (microarchitecture). The same ISA can have radically different microarchitecture implementations.

graph TB
    subgraph "Software Layer"
        A[High-Level Languages C/C++/Rust]
        B[Compiler]
        C[Assembly Language]
    end
    subgraph "ISA Contract Layer"
        D[Instruction Set Architecture]
    end
    subgraph "Hardware Layer"
        E[Microarchitecture Impl. A]
        F[Microarchitecture Impl. B]
        G[Microarchitecture Impl. C]
    end

    A --> B --> C --> D
    D --> E
    D --> F
    D --> G

    style D fill:#fff9c4,stroke:#f9a825

2. ISA Classification

2.1 By Operand Location

Type Operand Source Example
Stack architecture Operands implicit on stack top JVM bytecode
Accumulator architecture One operand implicit as accumulator Early x86
Register-memory One operand can come from memory x86
Register-register (Load-Store) Operands must be in registers ARM, RISC-V, MIPS

2.2 CISC vs RISC

graph LR
    subgraph "CISC Design Philosophy"
        C1[Complex instructions]
        C2[Variable-length encoding]
        C3[Instructions can directly access memory]
        C4[Rich addressing modes]
        C5[Microcode implementation]
    end

    subgraph "RISC Design Philosophy"
        R1[Simple instructions]
        R2[Fixed-length encoding]
        R3[Load-Store architecture]
        R4[Few addressing modes]
        R5[Hardwired control]
    end

    C1 ---|Contrast| R1
    C2 ---|Contrast| R2
    C3 ---|Contrast| R3
Feature CISC (x86) RISC (ARM/RISC-V)
Instruction length Variable (1-15 bytes) Fixed (4 bytes)
Instruction count Thousands Hundreds
Memory access Any instruction can access memory Only Load/Store
Register count Fewer (x86: 16 GPR) More (ARM: 31, RISC-V: 32)
Decode complexity High (requires microcode) Low (hardwired)
Code density Higher Lower (but Thumb-2/RVC mitigate)

Modern Convergence

Modern x86 processors internally decode CISC instructions into micro-ops, essentially executing RISC-style operations at the microarchitecture level. The CISC vs RISC boundary has blurred at the microarchitecture level.

3. Major ISAs in Detail

3.1 x86 / x86-64

  • History: Intel 8086 (1978) -> IA-32 -> AMD64/x86-64
  • Characteristics: Extremely strong backward compatibility; variable-length instruction encoding (prefix + opcode + ModR/M + SIB + displacement + immediate)
  • Extensions: SSE -> AVX -> AVX-512 (SIMD vector extensions)
  • Ecosystem: Dominant in desktop and server markets

3.2 ARM (AArch64 / ARMv9)

  • Characteristics: Fixed 32-bit instructions; conditional execution; high energy efficiency
  • Registers: 31 64-bit general-purpose registers (X0-X30) + SP + PC
  • Extensions: NEON (SIMD), SVE/SVE2 (scalable vector)
  • Ecosystem: Dominant in mobile devices; Apple Silicon and AWS Graviton entering desktop/server

3.3 RISC-V

  • Origin: UC Berkeley, launched in 2010
  • Core advantage: Open-source, modular, extensible

RISC-V adopts a modular design:

Module Name Function
RV32I/RV64I Base integer 47 base instructions
M Multiply/Divide Integer multiplication and division
A Atomics Atomic memory operations
F/D Floating-point Single/double precision floating-point
C Compressed 16-bit compressed instructions
V Vector Scalable vector extension

Common combination: RV64GC = RV64I + M + A + F + D + C

Significance of RISC-V

RISC-V is to processors what Linux is to operating systems -- an open-source ecosystem breaking the ISA monopoly and lowering the barrier to chip design.

4. Instruction Encoding

Taking RISC-V RV32I as an example, all instructions are fixed at 32 bits with 6 basic formats:

R-type: [funct7(7)] [rs2(5)] [rs1(5)] [funct3(3)] [rd(5)] [opcode(7)]
I-type: [imm[11:0](12)]         [rs1(5)] [funct3(3)] [rd(5)] [opcode(7)]
S-type: [imm[11:5](7)] [rs2(5)] [rs1(5)] [funct3(3)] [imm[4:0](5)] [opcode(7)]
B-type: [imm(7)]       [rs2(5)] [rs1(5)] [funct3(3)] [imm(5)]      [opcode(7)]
U-type: [imm[31:12](20)]                              [rd(5)] [opcode(7)]
J-type: [imm(20)]                                     [rd(5)] [opcode(7)]

Design principles:

  • rs1, rs2, rd are in fixed positions across all formats -> simplifies decode hardware
  • opcode and funct3/funct7 combinations determine the specific operation
  • Immediates are sign-extended with the MSB always at bit 31 -> simplifies sign-extension circuitry

5. Addressing Modes

Addressing Mode Operand Source Example (RISC-V style)
Immediate Constant in the instruction addi x1, x2, 42
Register Register contents add x1, x2, x3
Base + offset Register + offset -> memory address lw x1, 8(x2)
PC-relative PC + offset beq x1, x2, label

RISC-V uses only these 4 addressing modes, maintaining simplicity. x86 supports more complex modes such as [base + index*scale + displacement].

6. Application Binary Interface (ABI)

The ABI defines:

  • Calling conventions: How arguments are passed (registers vs stack), return value location
  • Register usage rules: Caller-saved vs callee-saved
  • Stack frame layout: Local variables, return address, frame pointer

RISC-V ABI Register Conventions

Register ABI Name Purpose Saver
x0 zero Hardwired zero --
x1 ra Return address Caller
x2 sp Stack pointer Callee
x5-x7 t0-t2 Temporary registers Caller
x8 s0/fp Saved register / frame pointer Callee
x10-x17 a0-a7 Arguments / return values Caller
x18-x27 s2-s11 Saved registers Callee
x28-x31 t3-t6 Temporary registers Caller

7. System-Level ISA Features

7.1 Privilege Levels

Modern ISAs define multiple privilege levels to isolate software layers:

Level RISC-V x86 Purpose
Highest privilege Machine (M) Ring 0 Firmware / Hypervisor
Intermediate Supervisor (S) Ring 0 OS kernel
Lowest User (U) Ring 3 User programs

7.2 Interrupts and Exceptions

  • Interrupt: External asynchronous event (I/O completion, timer)
  • Exception: Synchronous event during instruction execution (page fault, illegal instruction, system call)
  • Trap: Intentionally triggered exception (ecall / int 0x80 for system calls)

Handling flow: Save PC -> Switch privilege level -> Jump to handler -> Resume execution

7.3 Memory Model

Defines the visibility ordering of memory accesses in a multi-core environment:

  • Sequential Consistency: Most intuitive, high performance overhead
  • TSO (Total Store Order): x86 default, allows Store-Load reordering
  • Weak Ordering: ARM/RISC-V default, requires fence instructions to enforce ordering
\[ \text{SC} \subset \text{TSO} \subset \text{Weak Ordering} \]

(Constraints from strong to weak; performance potential from low to high)

8. ISA Design Trade-offs

Design Decision Trade-off
Fixed vs variable instruction length Simple decoding vs code density
More vs fewer registers Reduce memory access vs wider instruction encoding
Complex vs simple instructions More work per instruction vs pipeline-friendly
Strong vs weak memory ordering Simpler programming vs more hardware optimization opportunity
Specialized extensions vs general instructions Domain-specific performance vs ISA simplicity

Navigation

评论 #